Intel is internally evaluating a dual-sided power-delivery architecture using both wafer front- and back-side metallization for its 1.4nm-class process to help narrow the gap with foundry rivals. The company had planned an in-house back-side power-distribution network (BSPDN) called PowerDirect for the base 14A node; it is now assessing a hybrid front-and-back metal routing approach for 14A2. The shift is driven by lithography limits, notably random defects when shrinking the minimum metal-layer

Intel is internally evaluating a dual-sided power-delivery architecture using both wafer front- and back-side metallization for its 1.4nm-class process to help narrow the gap with foundry rivals. The company had planned an in-house back-side power-distribution network (BSPDN) called PowerDirect for the base 14A node; it is now assessing a hybrid front-and-back metal routing approach for 14A2. The shift is driven by lithography limits, notably random defects when shrinking the minimum metal-layer spacing (M0) toward about 21nm.