JCET said it has achieved a significant advance in high-aspect-ratio
through-silicon via (TSV) technology and, with partners, completed sample
fabrication. The TSV process targets 2.5D/3D advanced packaging, silicon
interconnects and heterogeneous integration, intended to strengthen JCET’s
microsystem integration process capabilities and provide one-stop manufacturing
support for system-level integration of high-compute, high-memory chips.